The present invention relates generally to phase-lock loop circuits and, more particularly, to such circuits having frequency detectors for fast lock acquisition.
Phase lock loops (hereinafter referred to as "PLLs") are often employed with data communications equipment such as frequency and signal synthesizers and jitter measurement circuits. With PLLs having narrow, flat gain bandwidths on the order of 1 Hz, stability constraints result in a lock acquisition time for phase-lock which can be several seconds. In present high speed circuits, this represents a considerable delay.
Second order phase-lock loops typically include frequency detector or comparator means to assist in acquiring lock when an extended range of input data signal frequencies is expected. Such a conventional PLL circuit is shown in block diagram form in FIG. 1. Frequency detector 10 and phase detector 15 each receive frequency signals f.sub.1 and f.sub.2. Frequency f.sub.1 is of the system input data signal and f.sub.2 is of the reference signal generated by voltage controlled oscillator (hereinafter referred to as "VCO") 30. Frequency detector 10 and phase detector 15 may be referred to generally as the PLL input stage and serve to compare the frequency and phase of signals f.sub.1 and f.sub.2, respectively. The frequency and phase difference between these signals is used to generate error signals V.sub.f and V.sub.d, respectively, which are fed back to VCO 30 through loop filter 20 to control the frequency f.sub.2 so as to reduce the phase and frequency difference with respect to f.sub.1. As will be readily understood by those skilled in the art, frequency detector 10 provides a coarse tuning of VCO 30, and phase detector 15 provides a fine tuning of VCO 30.
Frequency synthesizers and jitter measurement circuits often employ a PLL having a bandwidth on the order of 1 Hz. Even with frequency detectors, the lock acquisition time for such conventional PLLs is typically greater than ten seconds. While such a long acquisition time is satisfactory for machine-only environments, it is desirable to reduce waiting time to fractions of a second when human operators are involved.
Lock acquisition time for PLLs is largely a function of the loop filter response to frequency and phase difference signals from the corresponding detector means. FIG. 2 shows a schematic diagram of a conventional loop filter 20 suitable for use in the PLL circuit of FIG. 1. Operational amplifier 22 has its positive terminal grounded, and input signal voltage V.sub.d from phase detector 15 connected to its negative terminal across resistor 24. Input signal voltage V.sub.f from frequency detector 10 is connected to capacitor 28 in the feedback loop across resistor 25 and to the negative terminal of operational amplifier 20 across resistors 25 and 26 in series. Loop filter 20 provides control voltage V.sub.c to VCO 30 to reset f.sub.2 to match the system input signal f.sub.1.
In order to acquire lock, capacitor 28 must be charged to a voltage that will set the VCO to the proper frequency. The frequency detector is primarily responsible for charging capacitor 28. For PLLs with a narrow bandwidth and wide input frequency range, capacitor 28 must be larger and, thus, it often takes a longer time to charge. It has been found that modifying the frequency detector will permit modification of this charging time.
Combined phase and frequency detectors in PLLs have been employed to aid in lock acquisition and have been realized through the use of up-down counters. The output voltage versus frequency characteristic of such devices when employed as a frequency detector in a PLL is shown graphically in FIG. 3. While a signal representing the sign of the frequency difference of the input data and clock signals is provided, such a device gives little or no indication of the magnitude of the difference in frequency. As a result, capacitor 28 is charged at a generally constant rate, and the acquisition time is proportional to the initial frequency difference detected. Mathematically, the relationship may be represented by: EQU T.sub.p =2.DELTA.f/(.pi..sup.2 f.sub.BW) Eq. 1
where T.sub.p is the acquisition time, .DELTA.f is the initial detected frequency difference, and f.sub.BW is the PLL bandwidth.
T.sub.p can be reduced by amplifying frequency detector output signal V.sub.f to charge capacitor 28 sooner. It has been suggested alternatively (because of the different technologies involved) to achieve this by increasing the pulse rate of V.sub.f or by increasing the signal amplitude of V.sub.f as the frequency difference increases. However, if V.sub.f becomes too large when f.sub.1 is approximately equal to f.sub.2, the PLL will overshoot the lock region and become unstable. To make V.sub.f larger overall but small where f.sub.1 -f.sub.2 is approximately zero, V.sub.f should be made proportional to f.sub.1 -f.sub.2. Prior PLL devices, such as the quadricorrelator and the rotational frequency detector, have attempted to do this, but have only been successful within a relatively small frequency range. FIG. 4 shows graphically the output voltage versus frequency characteristics for these devices when employed as frequency detectors in a PLL.
As can be seen, V.sub.f is proportional to f.sub.1 -f.sub.2 only over a small frequency difference of approximately .+-.25%. In this range the acquisition time can be expressed as: EQU T.sub.p =(4.pi.f.sub.BW).sup.-1 ln(.DELTA.f/2.pi.f.sub.BW) Eq. 2
This logarithmic function of .DELTA.f grows relatively slowly. For example, if f.sub.BW =1 Hz and .DELTA.f=50 Hz, then T.sub.p= 0.17 seconds. Under the same conditions, the frequency detector represented by Equation 1 would result in an acquisition time of ten seconds. If .DELTA.f is increased to 100 Hz, the device of Equation 2 would have a T.sub.p of 0.22 seconds while the device of Equation 1 would have a T.sub.p of 20 seconds. Thus, such quadricorrelator devices perform satisfactorily if .DELTA.f is approximately less than one quarter of f.sub.1.
However, if .DELTA.f becomes greater that f.sub.1 /2, quadricorrelator and rotational frequency detectors cannot be used in PLLs to effectively charge capacitor 28 and acquire phase-lock. Therefore, it is desirable to provide a frequency detector wherein V.sub.f is proportional to f.sub.1 -f.sub.2 over an extended range.
An object of the present invention is to provide a frequency comparator for phase-lock loop circuits having fast lock acquisition time.
Another object of the present invention is the provision of a frequency detector in a phase-lock loop circuit whose output voltage signal is proportional to the difference between the frequencies of its input signals over an extended frequency range.
A further object of the present invention is the provision of a combined phase and frequency comparator for a plurality of input periodic waveforms having fast lock acquisition time and increased loop stability.
These and other objects of the present invention are attained in the provision of a PLL frequency detector or comparator having an up-down counter, responsive to beat signals produced by the input periodic waveforms of the VCO reference signals and the input data signals, to produce top and bottom output signals which enable multivibrators connected to each of the input signal lines to transmit overflow and underflow output pulses, whose average is proportional to the difference in frequency of the input signals up to a predetermined maximum level, as control signals for the PLL loop filter. The up-down counter may also include three or more states with buffer states which prevent generation of overflow or underflow output signals when the PLL is within a predetermined region of phase-lock and the sign of the beat signal oscillates. The up-down counter may also be employed simultaneously as a phase detector or comparator, wherein the top and bottom output signals are combined so as to produce control signals for the PLL loop filter when the overflow and underflow output signals are not generated.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.